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TOE10G-IP core10GbE TCP/IP stack implementation by all hW logic, without CPU

TOE10G-IP

10GbE TCP Off-loading Engine(TOE10G-IP) IP core is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE10G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Intel FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel FPGA boards. You can evaluate TOE10G-IP core on real board before purchasing.

All HW Logic without CPU 1000Mbps TOE1G-IP

TOE2 IP

TOE1G-IP core


Specification Comparison of TOE-IP series and how to choose suitable solution for your application: Click Here

Features

  • 10GbE TCP/IP stack implementation
  • Support IPv4 protocol
  • Support one port connection
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 156.25 MHz clock frequency
  • Support Multi-session (8 Sessions Reference design is available)
  • Provide free evaluation demo file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram



Document & Demo file download

Document Name Revision
TOE10G-IP core Presentation 1.1E
Document Name Arria10 SoC
TOE10G-IP core Datasheet Rev1.0
Half
Duplex
Reference Design Document Rev1.0
Demo Instruction Document Rev1.1
Evaluation file & Apps for PC
Get Password
Arria10 SoC
Demo Video
Full
Duplex
Reference Design Document Rev1.0
Demo Instruction Document Rev1.1
Evaluation file & Apps for PC
Get Password
Arria10 SoC
Demo Video
Multi Session Reference Design Document Rev1.0
Demo Instruction Document Rev1.0
Evaluation file & Apps for PC
Get Password
Arria10 SoC
Demo Video


Support Multi-Session!!


TOE10G-IP core is compact resource. It achieves multi-session by implementing multiple cores in FPGA. Total performance does not drop even the number of sessions increases.
You can free evaluate TOE10G 8 session demo bit file on Intel FPGA boards.





Free sof file for evaluation to able to see the performance

DesignGateway provide 1-hour limitation sof file for Arria10 SoC FPGA Development Kit. You can evaluate TOE10G-IP core on real board before purchasing.







Inquiry/Purchase

Part Number Supported Devices
TOE10G-IP-A10 Arria 10


Application example

TOE10G-IP core is the vest solution for large-scale and high-speed data transmission applications such as image/video streaming or data storage
Large scale Blade Server NAS SDN (Software Defined Network) Video Editing System


Specification Comparison of TOE-IP series and how to choose suitable solution for your application : Click Here

Alliance Partner



Design Gateway Co., Ltd.

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