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TOE10G-IP core10GbE TCP/IP stack implementation by all hW logic, without CPU

TOE10G-IP

10GbE TCP Offloading Engine(TOE10G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE10G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE10G-IPcore on real board before purchasing.

All HW Logic without CPU 1000Mbps

TOE1G-IP core

Specification Comparison of TOE-IP series and how to choose suitable solution for your application: Click Here

Features

  • 10GbE TCP/IP stack implementation
  • Support IPv4 protocol
  • Support one port connection
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 156.25 MHz clock frequency
  • Support Multi-session (8 Sessions Reference design is available)
  • Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram



Document & Demo bit file download

Document Name Revision
TOE10G-IP core Presentation 1.2E

Document Name Zynq-7000
ZC706
Kintex-7
KC705
Virtex-7
VC707
TOE10G-IP core Datasheet Rev1.3
Half
Duplex
Reference Design Document Rev1.0
Demo Instruction Document Rev1.2
Full
Duplex
Reference Design Document Rev1.0
Demo Instruction Document Rev1.1
Evaluation bit file & Apps for PC
Get Password
ZC706 KC705 Rev1.1 & later VC707
KC705 Rev1.0
Demo Video

Multi
Session
Reference Design Document Rev1.0
Demo Instruction Document Rev1.0
Evaluation bit file & Apps for PC
Get Password
ZC706/KC705/VC707
Demo Video


Support Multi-Session!!


Max. 55 Sessions
can be implemented
in KCU105(XCKU040-2FFVA1156E)!!
TOE10G-IP core is compact resource. It achieves multi-session by implementing multiple cores in FPGA. Total performance does not drop even the number of sessions increases.
You can free evaluate TOE10G 8 session demo bit file on Xilinx FPGA boards.






Free bit file for evaluation to able to see the performance

TOE10G-IP Performance Test
on KC705/VC707
Video Clip on Youtube
DesignGateway provide 1-hour limitation bit file for FPGA Development Kits (KC705, VC707 and ZC706). You can evaluate TOE10G-IP core on real board before purchasing.

You also can watch the performance over 1GB/s data transmission from Youtube.





AB15-SFPFMC
DesignGateway also provide AB15-SFPFMC which has 4ch SFP+ interfaces.














Inquiry/Purchase

Part Number Supported Devices
TOE10G-IP-KT7 Kintex-7
TOE10G-IP-VT7 Virtex-7
TOE10G-IP-ZQ7 Zynq-7000
Accessories for evaluation Description
AB15-SFPFMC SFP-FMC adapter board for Xilinx FPGA boards.
SPF+ interface 4ch
On board 312.5MHz Clock Oscillator
User Manual


Application example

TOE10G-IP core is the vest solution for large-scale and high-speed data transmission applications such as image/video streaming or data storage
Large scale Blade Server NAS SDN (Software Defined Network) Video Editing System


.




Specification Comparison of TOE-IP series and how to choose suitable solution for your application : Click Here

Alliance Partner


Design Gateway Co., Ltd.

Head Office
3-23-17 Naka-cho, Koganei, Tokyo, JAPAN
R&D
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