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UDP10G-IP coreUDP/IP stack implementation by all hardware logic, without CPU

UDP10G-IP

UDP10G IP core is the epochal solution implemented without CPU. This IP core is suitable for network application. This IP product includes reference design for Intel® FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Intel® FPGA boards. You can evaluate UDP10G-IP core on real board before purchasing.


Features

  • All hardware logic to achive CPU-less system
  • Support IPv4 protocol
  • Support one port connection
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 125 MHz clock frequency
  • Provide free evaluation sof file for FPGA Development Kits (1 hour time limited)
  • Rerference design is included in IP core product


Block diagram




Document & Demo bit file download

Common Documents

Document name Revision
UDP10G-IP core Presentation

Document Name Arria® 10 SX
UDP10G-IP core Datasheet Rev1.0
Reference Design Document Rev1.0
Demo Instruction Document Rev1.0
Evaluation bit file & Apps for PC Arria® 10 SX
Demo Video

Free bit file for evaluation

DesignGateway provide 1-hour limitation sof file for Intel® FPGA Development Boards. You can evaluate UDP10G-IP core on real board before purchasing.


Inquiry/Purchase

Part Number Supported Devices
UDP10G-IP-A10 Arria® 10

Performance