FPGA Setup for LL10GEMAC-IP Loopback Test

Rev1.0 30-Jun-23

 

1      Test environment setup. 1

2      Revision History. 5

 

 

This document describes how to setup FPGA board and prepare the test environment for running LL10GEMAC-IP loopback demo for measuring the latency time. User sets test parameter on FPGA board and monitors the hardware status via NiosII command shell. More details of the demo are described as follows.

 

 

1       Test environment setup

 

Before running the test, please prepare following test environment.

 

Note: The latency time in the test depends on clock phase shift characteristic when the board boots up. Reset button is designed to reset the system which will change clock phase shift characteristic. Therefore, the user can press Reset button and may get the different latency time on the test.

 

 

Figure 11 LL10EMAC-IP demo on Arria10 GX

 

 

The step to setup test environment by using FPGA and PC is described in more details as follows.

 

1)    Turn off power switch and connect power supply to FPGA board.

2)    Connect micro USB cable between FPGA board and PC for FPGA configuration and JTAG UART.

 

 

Figure 12 Power and USB connection

 

 

3)    (Optional for running external loopback mode) Plug-in SFP+ Loopback cable.

4)    Turn on power switch on FPGA board.

5)    Open QuartusII Programmer to program FPGA through USB-1 by following step.

a)    Click “Hardware Setup…” to select USB-BlasterII[USB-1].

b)    Click “Auto Detect” and select FPGA device.

c)    Select FPGA device icon.

d)    Click “Change File” button, select SOF file in pop-up window, and click “open” button

e)    Check “program”

f)      Click “Start” button to program FPGA

g)    Wait until Progress status is equal to 100%

 

 

Figure 13 FPGA Programmer

 

 

6)    On Nios II command shell,

a.    Type “nios2-terminal”.

b.    Input ‘0’ or ‘1’ to initialize demo in external loopback mode or internal loopback mode.

 

 

Figure 14 Message after system boot-up

 

 

c.     After User select mode, the system initialization begins. Then, the main menu is displayed on NiosII command shell after the initialization is finished.

 

 

Figure 15 Initialization complete

 

 

Note: When running Internal loopback mode, SFP+ Loopback module is not used.

 

 

2       Revision History

 

Revision

Date

Description

1.0

26-Mar-21

Initial version release