TOE-IPcore

Support Gigabit Ethernet

TCP Offloading Engine(TOE) IPcore is the epochal solution implemented on low-cost processor. Usually TCP processing is complicated and needs expensive high-end CPU. Because TOE-IPcore automatically takes over some functions of TCP/IP protocol which needs high-speed operation instead of, It drastically reduces CPU load for host processor.

DesignGateway provide demo bit file for Xilinx Spartan-3A DSP 1800, ML506, ML605 and SP605 board for evaluation. You can evaluate TOE-IPcore on real board before purchasing. Go to Performance/Application

TOE(R)-IP <Rx side> is also released!! Go to TOE(R)-IP page

Features of TOE-IPcore

• Insert the IPcore between Ethernet MAC and Host processor.
• Functions: TCP sequence number auto generation, TCP check sum. and auto insert, resend window buffer and data, IP header check sum auto generation, IP header auto generation, etc.
• Data FIFO port is separated. The written data is combined with header and sent as TCP packet.
• Support IPv4 （Able to support IPv6）
• Support jumbo frame.
• External RAM is not required.
• Support window size from 2kbyte to 64kbyte （Use BRAM）
• Provide ealuation bit file for Spartan3-A DSP 1800, ML506, ML605 and SP605 board.（For other board, please ask DesignGateway.）
• Prepare rerference design using Xilinx Gigabit Ethernet MAC core and MicroBlaze