Breaking Latency Barriers in Stock Trading with AMD AAT and DG Low-Latency IP cores Blog Article |
The Enhanced AMD's Stock Trading (AAT) demo by integrating DG's Low-Latency IP cores Blog Article |
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DG LL 10G EMAC-IP with AMD’s AAT demo |
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DG LL UDP10GRx-IP 16 Sessions demo for FinTech |
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DG TOE10GLL-IP 32 Sessions demo |
Document name | Update (Revision) |
Presentation | 1.0E |
Brochure | 2.6EX |
IP core & Option | Datasheet | Reference Design Document | Demo Instruction Document | FPGA Board Setup | Free Evaluation demo file Contact Us | |
Accelerated Algorithmic Trading (AAT) Demo |
Rev2.0 | Rev1.1 | U50 U250 |
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LL 10GEMAC-IP | Rev1.2 | Rev1.1 | Rev1.1 | Rev1.0 | ZCU102 | |
Accelerated Algorithmic Trading (AAT) Demo |
Rev1.1 | Rev1.2 | U50 U250 |
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LL UDP10GRx-IP | Rev2.0 | Rev1.2 | Rev1.2 | Rev1.1 | ZCU102 KCU116 |
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16 Session Demo | Rev1.0 | Rev1.0 | ZCU102 KCU116 |
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TOE10GLL-IP | Rev2.0 | Rev1.2 | Rev1.1 | ZCU102 ZCU106 |
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32 Session Demo | Rev1.0 | Rev1.0 | ZCU102 ZCU106 |