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TOE10G-IP core10GbE TCP/IP stack implementation by all hW logic, without CPU

TOE10G-IP

10GbE TCP Offloading Engine(TOE10G-IP) IPcore is the epochal solution implemented without CPU. Generally, TCP processing is so complicated that expensive high-end CPU is required. TOE10G-IP built by pure hardwired logic can take place of such extra CPU for TCP protocol management. This IP product includes reference design for Xilinx FPGA. It helps you to reduce development time.
DesignGateway provide demo file for Xilinx FPGA boards. You can evaluate TOE10G-IPcore on real board before purchasing.

All HW Logic TOE-IP core series

Features

  • 10GbE TCP/IP stack implementation
  • Support IPv4 protocol
  • Support one port connection
  • Support both Server and Client mode (Passive/Active open and close)
  • Support Jumbo frame
  • Transmit/Receive buffer size, programmable on HDL for optimized resource
  • Simple data interface by standard FIFO interface
  • Simple control interface by standard register interface
  • One clock domain interface by fixed 156.25 MHz clock frequency
  • Super low-latency DG 10G25G EMAC-IP (Option) Learn more
  • Support Multi-session (8 Sessions Reference design is available)
  • Provide free evaluation bit file for FPGA Development Kits (1 hour time limited)
  • Reference design is included in IP core product

Block diagram



Document & Demo bit file download

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Document Name Revision
TOE10G-IP core Leaflet Rev2.3
TOE10G-IP核 Leaflet (中文) Rev2.4CX
TOE10G-IP core Presentation 1.2E
DG EMAC-IP Presentation Rev1.0

Support Devices Zynq UltraScale+ ZCU106/ZCU102, Virtex UltraScale+ VCU118
Kintex UltraScale KCU105


Zynq-7000 ZC706, Virtex-7 VC707, Kintex-7 KC705
IP core & Option Datasheet Reference Design Document Demo Instruction Document Evaluation demo file ask password Demo Video
TOE10G-IP Rev1.12 Ultrascale/ZC706
Rev1.4
Ultrascale/ZC706
Rev2.1
FPGA board Setup Rev3.0
ZCU106
ZCU102
VCU118
KCU105
ZC706
VC707/KC705
Half DuplexRev1.0
Full DuplexRev1.0
VC707/KC705
Half DuplexRev1.2
Full DuplexRev1.1
VC707
KC705

VC707/KC705
10G25G EMAC-IP Rev1.3
FTP Server demo
with NVMe-IP
Rev1.1 Rev2.0
FPGA board Setup Rev3.0
ZCU106
KCU105
Multi Session Rev1.0 Rev1.0 ZC706
KC705
VC707


Super low-latency DG 10G25G EMAC IP core

DG 10G25GEMAC core implements the MAC layer for TOE10G-IP core and highly compatible with Xilinx MAC. It has many advantages.

  • Super low-latency, Tx=19.2nsec, Rx=44.8nsec.
  • Minimized resource usage, 1/2 of Xilinx MAC core.
  • Very low price, 1/5 of Xilinx MAC core.

DG 10G25GEMAC-IP Xilinx 10GEMAC
Tx latency (clk freq.=156.25MHz) 19.2ns (3clk) 19.2ns (3clk)
Rx latency (clk freq.=156.25MHz) 44.8ns (7clk) 115.2ns (18clk)
CLB LUTs 1873 3498
CLB Registers 1072 3291
CLB 326 694

Support Multi-Session!!


Max. 55 Sessions
can be implemented
in KCU105(XCKU040-2FFVA1156E)!!
TOE10G-IP core is compact resource. It achieves multi-session by implementing multiple cores in FPGA. Total performance does not drop even the number of sessions increases.
You can free evaluate TOE10G 8 session demo bit file on Xilinx FPGA boards.






Free bit file for evaluation to able to see the performance

TOE10G-IP Performance Test
on KC705/VC707
Video Clip on Youtube
DesignGateway provide 1-hour limitation bit file for FPGA Development Kits (KC705, VC707 and ZC706). You can evaluate TOE10G-IP core on real board before purchasing.

You also can watch the performance over 1GB/s data transmission from Youtube.





AB15-SFPFMC
DesignGateway also provide AB15-SFPFMC which has 4ch SFP+ interfaces.















Application example

TOE10G-IP core is the vest solution for large-scale and high-speed data transmission applications such as image/video streaming or data storage
Large scale Blade Server NAS SDN (Software Defined Network) Video Editing System



Alliance Partner


Design Gateway Co., Ltd.

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