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tCAM IP core achieves Ultra High-speed Matching & Filtering

Design Gateway tCAM IP is a high performance, extremely low latency and highly configurable ternary content-addressable memory IP. tCAM-IP can make deterministic search at 200MSPS continuously speed with constant latency at 7 clock cycles. It can achieve matching/filtering performance at 200,000,000 packets per second over 40G/100G Ethernet. We can provide tCAM-IP custom reference design together with TOE-IP, UDP-IP and EMAC-IP based on customer requirements. Contact Us Blog Article: What's tCAM?
tCAM IP for Xilinx	tCAM IP for Intel
tCAM-IP performance demo on KCU116	tCAM-IP performance demo on Arria 10 SX
Features Key width 64/56/48/40/32/24/16 bits Up to 1M rule entries Searching latency is constant at 7 clock cycles Up to 200 MSPS @ 200MHz searching speed, 1,000,000 Search/MHz Easy to customize rule table memory Simple rule table memory setup and user interface signals Free evaluation demo combined with DG TOE1G-IP core is available	Target Application Network packet filtering/forwarding Intelligent switch/router Deep Packet Inspection (DPI) Big data filtering
	tCAM-IP Introduction

Application Specific IP Cores Low Latency Networking IPs for Fintech Design Gateway’s Low Latency (LL) Networking IP is designed from the ground up for very low latency requirements. Especially, FinTech applications such as high-frequency trading (HFT), high speed trading (HST), Market Data Processing and Tick-to-Trade (T2T) systems. We can provide total solutions for low latency Networking IP cores and FPGA logic customization for application specific requirements. We can provide LL TOE10G-IP, LL UDP10G-IP, LL EMAC-IP Learn more SHA-256 IP SHA-256 IP is an optimized and efficient implementation of a secure hash algorithm SHA-256 specified in FIPS 180-4 standard. SHA256-IP can process 512-bit data blocks in just 65 clock cycles. Delivering 7.875Mbps throughput per 1MHz clock such as 1.575 Gbps throughput @ 200MHz.Learn more AES-128 IP AES-128 IP is 1st member of Advanced Encryption Standard (FIPS-197) IP Series, designed to support ECB mode for both encryption and decryption. AES128-IP computes 128-bit data blocks within constant 11 clock cycles. Delivering 11.6Mbps throughput per 1MHz clock such as 2.9 Gbps throughput @ 250MHz.Learn more Recommended Articles Design Gateway's Technology Blog Technology introduction articles related to DG products. What’s TCAM? AES (Advanced Encryption Standard) IP Cores Super low latency TOE 10G IP Super Low-Latency EMAC Technical Updates The latest Technical Documents Update TOExxG-IP Presentation (Intel/Xilinx) UDP100G-IP New Release (Xilinx) tCAM-IP New Release (Xilinx) | DG | About Us | Privacy | Unsubscribe/Address change | Contact | (c) 2021 Design Gateway Co., Ltd.