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Fully CPU offload for TCP/IP transmission for 1G/10G/25G/40G and up to 100G
Learn more about TOE-IP series for Intel \| Learn more about TOE-IP series for Xilinx

TCP Offloading Engine IP Core provides the full hardware TCP/IP protocol stack engine which is the epochal solution implemented without CPU. TCP/IP function is enable by just controlling simple FIFO interfaces. You can choose suitable line rates from 1G-100Gbps. The latest generation of DG's TOE100G-IP is capable of full TCP/IP offload and able to achieve 12GB/s without CPU required. Check out our TOE IP Core & see its incredible performance.

Overcoming the 100G performance bottleneck with TOE100G-IP

To overcome the CPU and main memory bottleneck on host processor systems that limits TCP performance, we propose a solution that uses pure hardware logic TOE IP cores. Our solution can handle single or multiple TCP sessions and achieve near-optimal TCP throughput of almost 10GB/s over 100G bandwidth. Our solution is ideal for applications that require FPGA acceleration for very high data rates over 100G without CPU intervention.

Applications

	High throughput data streaming over up to 100G Smart city video surveillance Smart automation control and monitoring Aerospace and defense radio or radar signals Healthcare medical images
	Multiple data channel transmission between FPGA & Host systems FPGA-based applications often use FPGA to capture data from multiple channels and send it over the network. We provide a proven reference design for multi-session TOE-IP that can help you reduce your development time and achieve very high TCP performance in your systems.

TOE IP core series YouTube Videos

Design Gateway YouTube channel provides introductions and performance demos of ultra-fast network IPs, storage IPs, and security IPs. Subscribe to DG IP core YouTube channel
TOE100G-IP Performance demo on Intel Agilex F-Series [12GB/sec]	TOE100G-IP : Multi-session performance demo on KCU116 [4 sessions \| 9182MB/sec]