FPGA Setup for 2-ch RAID0 by NVMe-IP Series Demo

1 Overview

This document outlines the setup procedure and testing environment for demonstrating a 2-channel RAID0 configuration using NVMe IP cores developed by Design Gateway. The setup operates on an FPGA development platform and supports both PCIe Gen3 and Gen4 interfaces. In this configuration, two NVMe SSDs are connected to the FPGA board through Design Gateway adapter boards. These adapter solutions accommodate PCIe or FMC interfaces, allowing flexible deployment based on the FPGA development board in use. To ensure optimal RAID0 operation, it is recommended to use two identical SSD models. Matching the SSDs helps maintain synchronized data access latencies and throughput.

2 Environment Requirements

To successfully run the 2-ch RAID0 NVMe-IP demo on FPGA, ensure the following components are prepared:

1) Supported FPGA Development Boards:

· PCIe Gen4 (Hard IP): VCK190

· PCIe Gen4 (Soft IP): VCU118, ZCU106

· PCIe Gen3 (Hard IP): KCU105

· PCIe Gen3 (Soft IP): ZCU106, ZCU102, KCU116

2) The PCIe adapter board provided by Design Gateway, required to interface NVMe SSDs with the FPGA board:

https://dgway.com/ABseries_E.html

· AB17-PCIeX16: M.2-FMC adapter board

· AB18-PCIeX16: PCIe x16 Lanes Crossover adapter board

· AB19-M2PCI: M.2-PCIe adapter board

· AB20-U2PCI: U.2/U.3-PCIe adapter board

3) Quad M.2 expansion card, required when using the AB18-PCIeX16 to connect multiple M.2 SSDs.

4) Two NVMe SSDs installed into the adapter board or the Quad M.2 card.

5) Power supply

· ATX power supply for powering the PCIe adapter board if required.

· Power adapter for the FPGA development board.

6) USB cable for FPGA programming and Serial console, connecting between FPGA board and PC.

· VCK190: One USB Type-C cable

· Other boards: Two micro-USB cables

7) PC installing FPGA programmer software (Vivado) and Serial console software such as TeraTerm or HyperTerminal.

Figure 1 NVMe IP Series RAID0x2 Demo Setup by AB17 on VCK190

Figure 2 NVMe IP Series RAID0x2 Demo Setup by AB18 on VCU118

Figure 3 NVMe IP Series RAID0x2 Demo Setup by AB17 on ZCU106

Figure 4 NVMe IP Series RAID0x2 Demo Setup by AB17 on ZCU102

Figure 5 NVMe IP Series RAID0x2 Demo Setup by AB17 and AB19 on KCU116

Figure 6 NVMe IP Series RAID0x2 Demo Setup by AB17 on KCU105

3 Demo Setup

3.1 Hardware Setup

1) Ensure that the power switch on the FPGA board is turned OFF.

2) Check DIP switch setting for JTAG configuration on Zynq and Versal board.

· For ZCU106/ZCU102 board, set SW6=all ON to config PS from JTAG, as shown in Figure 7.

Figure 7 SW6 Setting on ZCU106/ZCU102

· For VCK190 board, set SW11= all OFF in order to not use micro SD card to boot, as shown in Figure 8.

Figure 8 SW11 Setting on VCK190

3) Prepare the NVMe SSD and the appropriate PCIe Adapter board based on your hardware configuration.

AB17-M2FMC

Connect two M.2 NVMe SSDs to AB17 and then connect AB17 to HPC on KCU105 (J22), HPC-1 on ZCU106 (J5), HPC-0 on ZCU102 (J4), or FMCP-1 on VCK190 (J51), as shown in Figure 9

Figure 9 Connect NVMe SSDs to AB17-M2FMC

AB18-PCIeX16 with Quad M.2 card

i) Verify that two mini jumpers are inserted on the J5 connector of the AB18 board.

Figure 10 Check Jumper on AB18

ii) Connect the ATX power supply to the AB18 board.

Figure 11 Connect ATX Power Supply to AB18 Board

iii) Connect the A-side of the AB18 board to the PCIe connector on the FPGA board.

Figure 12 Connect AB18 Board to FPGA Board

iv) Connect two M.2 NVMe SSDs to Quad M.2 card.

Figure 13 Connect NVMe SSDs to AB17-M2FMC

v) Connect the Quad M.2 card to the B-side of the AB18 board.

Figure 14 Connect Quad M.2 card to AB18 Board

AB19-M2PCI

i) Confirm that two mini jumpers are inserted at JP1, specifically between pins 1-3 and 2-4.

ii) Connect the NVMe SSD to CN1: PCIe Lane 3-0 and CN2: PCIe Lane 7-4 on the AB19 board.

iii) Connect the 6-pin PCIe AUX power cable from the ATX power supply to the AB19 board.

Figure 15 Prepare AB19

iv) Insert the AB19 board into the PCIe connector on the FPGA board.

Figure 16 Connect AB19 to FPGA Board

v) Adjust the height of the AB19 by sliding the support board up or down until it is properly aligned with the PCIe connector on the FPGA board. Once aligned, tighten the wing nut to secure it in place.

Figure 17 Adjust Height of AB19 Support Board

AB17-M2FMC and AB19-M2PCI

For KCU116, both the AB17-M2FMC and AB19-M2PCI adapter boards are required to connect two M.2 NVMe SSDs.

· The first NVMe SSD is connected to Drive#1 on the AB17-M2FMC.

· The second NVMe SSD is connected to connector CN2 (PCIe Lane 7-4) on the AB19-M2PCI.

This setup is illustrated in Figure 18. Detailed connection instructions for each adapter board are provided in the previous sections titled AB17-M2FMC and AB19-M2PCI.

Figure 18 Insert two M.2 NVMe SSDs to Drive#1 of AB17 and CN2 of AB19

4) Connect USB cable between FPGA board and PC for FPGA programming and Serial console as shown in. Figure 19

· VCK190: Connect one USB type-C cable.

· Others boards: Connect two micro-USB cables.

Figure 19 USB Cable Connection

5) Power on the system.

i) Turn on the power switch on the PCIe adapter board.

ii) Turn on the power switch on the FPGA board.

Figure 20 Turn on Power Switch

3.2 Software Setup

1) When connecting the FPGA board to a PC via USB, identify the correct COM port for Serial communication:

· VCU118, KCU116, KCU105: Select the Standard COM port

· VCK190, ZCU106, ZCU102: Select the lowest-numbered COM port from the additional ports that appear after connection.

Figure 21 Additional COM Port

2) Use a Serial console application (e.g., Tera Term) to establish a connection with the FPGA board. Apply the following configuration: Baud rate=115,200, Data=8 bits, Parity=None, and Stop bits=1, as shown in Figure 22.

Figure 22 Series Console Setting

3) For KCU105 board connected via the AB17, the Enhanced COM port must be used to access the System Controller menu. Configure the console with the same settings as above (Buad Rate:115200, Data: 8-bit, No parity, Stop:1). Once connected, follow these steps to set the FMC VADJ voltage to 1.8V:

i) Input ‘4’ to select Adjust FMC Settings.

ii) Input ‘4’ to set FMC VADJ to 1.8V.

iii) Input ‘0’ to return to Main Menu.

iv) Input ‘2’ to get PMBUS Voltages.

v) Input ‘7’ to get VADJ1V8 Voltage. The output must show exactly 1.8V to confirm that the VADJ has been set completely.

For detailed information on the System Controller interface, refer to the “UG917-KCU105 Board User Guide” in section “Appendix C: System Controller”.

https://www.xilinx.com/support/documents/boards_and_kits/kcu105/ug917-kcu105-eval-bd.pdf

Figure 23 Setting VADJ on FMC for KCU105

4) Program configuration file to FPGA board.

· For VCU118, KCU116, and KCU105: open Vivado tool and use the Hardware Manger to program the configuration file (.bit) to the FPGA. Refer to Figure 24 for detailed steps.

Figure 24 Programmed by Vivado

· For VCK190, ZCU106, and ZCU102: use Vivado TCL shell to run the batch file. Navigate to the directory containing the downloaded batch file, and run the appropriate script by typing: “NVMeXXRaid0x2Test_ <board_name>.bat”, as shown in Figure 25.

Figure 25 Downloaded by Command Script on Vivado TCL Shell

5) After programming the FPGA, both LED[0] and LED[1] should be ON during initialization. Once the NVMe-IP completes initialization, LED[1] will turn OFF, as illustrated in Figure 26. For more information on LED behavior, refer to Table 1.

Table 1 LED Definition

GPIO LED	ON	OFF
0	Normal operation	Clock is not locked
1	System is busy	Idle status
2	PCIe error detected	Normal operation
3	Data verification fails	Normal operation

Figure 26 LED Status When the Initialization is Complete

6) Once the FPGA is initialized, a welcome message and the main menu will be displayed on Series console. The system is now ready to receive user commands.

Figure 27 Welcome Message and Main menu

4 Revision History

Revision	Date (D-M-Y)	Description
2.03	18-Jun-25	Include AB19 and KCU116 board support
2.02	3-Aug-22	Include NVMe-IP for Gen4 and support VCK190 board
2.01	15-Jul-21	Include NVMeG4-IP demo
2.00	29-Jun-20	Remove demo instruction from the document and add NVMeG3-IP
1.00	9-Oct-17	Initial version release