Core Facts
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Documentation	User Guide, Design Guide
Design File Formats	Encrypted HDL
Instantiation Templates	VHDL
Reference Designs & Application Notes	Vivado Project, See Reference Design Manual
Additional Items	Demo on ZCU102, ZCU106, KCU105
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Features

· UDP/IP stack implementation

· Support IPv4 protocol

· Full-duplex transfer using distinct port numbers for Tx and Rx ports

· Support multiple sessions via multiple UDP40G IPs

· Support Jumbo frames

· Transmit packet size aligned to 256-bit, transmitted data bus size

· Total receive data size aligned to 256-bit, received data bus size

· Adjustable Transmit/Receive buffer sizes for resource and performance optimization

· Simple data interface by standard FIFO interface at 256-bit data bus

· Simple control interface by 32-bit single port RAM interface

· Ethernet MAC interface by 256-bit FWFT FIFO interface with provided adapter logic

· Recommended user clock frequency of at least 200 MHz

· Reference design available on ZCU102, ZCU106 and KCU105 evaluation boards

· Support IP fragmentation

· Customized services available for:

· Multicast IP

· Unaligned 256-bit data transferring

· Network parameter assignment through alternative methods

Table 1: Example Implementation Statistics

Family

Example Device

Fmax

(MHz)

CLB Regs

CLB LUTs

CLB¹

IOB

BRAMTile²

Design Tools

Zynq-Ultrascale+

XCZU9EG-FFVB1156-2

300

4032

3658

673

34.5

Vivado2022.1

Kintex-Ultrascale

XCKU040FFVA1156-2E

300

4032

3660

733

34.5

Vivado2022.1

Notes:

1) Actual logic resource dependent on percentage of unrelated logic

2) Block memory resources are based on 64KB Tx data buffer size, 16KB Tx packet buffer size, and 64KB Rx data buffer size.

Applications

Figure 1: UDP40G IP Application

The 40G Ethernet is a communication channel for transferring data with remote controlling system. When combined with the UDP/IP protocol, this system can transfer data in both Tx and Rx direction at high-speed rate via 40G Ethernet network. Additionally, UDP/IP supports data transfer for both one-by-one and broadcast systems. UDP40G IP is an integrated IP that enables data transfer via 40G Ethernet without requiring the use of CPU or external memory. It is suitable for applications that require high-speed data transfer for both Tx and Rx directions, such as video data streaming and real-time monitoring system using FPGA solutions.

Figure 1 shows an example application of video camera system, where video raw data from the camera is stored in a FIFO and forwarded to a remote system via 40G Ethernet using the UDP40G IP. The UDP40G IP supports full-duplex transfer simultaneously using different port numbers, allowing the Remote system to update the parameters for real-time controlling via 40G Ethernet while receiving the data from UDP40G IP via 40G Ethernet network.

General Description

Figure 2: UDP40G IP Block Diagram

The UDP40G IP core is a powerful hardware module designed to implement the UDP/IP stack and integrate seamlessly with adapter logic for 40G/50G Ethernet Subsystem interface, forming the lower-layer hardware. Its user interface consists of a Register interface for control signals and a FIFO interface for data signals.

To access up to 32 registers, the Register interface uses a 5-bit address. The registers store network parameters, commands, and system parameters. Each UDP40G IP employs two distinct sessions for bi-directional data transfer, with one session dedicated to each direction. Network parameters must be set before initiating the IP initialization process by de-asserting the reset signal. Once the reset operation and parameter initialization are concluded, the IP is ready for data transfer with the target device. Altering network parameters necessitates a reset process. The UDP40G IP offers three initialization modes for obtaining the MAC address of the target device, with detailed information available in the IP Initialization topic.

Data transfer with the user occurs via a 256-bit FIFO interface. However, the FIFO interface lacks byte enable functionality, so transmitted data from the user must be aligned to 256-bit. Packet length and the total amount of transmitted data must also align with this boundary. On the other hand, received data on the Rx FIFO I/F becomes accessible when at least one 256-bit data is available in the Rx data buffer. If the total received data is not aligned to 256-bit, the user must await the arrival of additional data to fill the remaining byte of 256-bit data for reading the Rx data buffer.

To accommodate diverse user system requirements, which may be prioritize memory resources or performance, the IP allows users to adjust buffer sizes. Two buffers, namely Tx data buffer and Rx data buffer, can be resized as per user configuration. Insufficient Tx data buffer size may lead to the UDP40G IP transmitting all data to the target before the user refills the buffer, resulting in a transmission pause until new data is supplied. On the other hand, an undersized Rx buffer may overflow if the user pauses data reading from the UDP40G IP for a long time, causing rejection of newly received packets from the target.

The UDP40G IP utilizes a 256-bit FWFT FIFO interface to connect with adapter logic designed for Ethernet MAC interface. This integration enables the UDP40G IP to operate in a single clock domain, aligning with the User logic’s clock domain. The adapter logic is included as part of the UDP40G IP reference design, provided as HDL code. It integrates two separate FIFOs for transferring data stream across different clock domains. This adapter logic can be shared when multiple UDP40G IPs are integrated for data transfer with various target devices. Further details regarding the internal hardware of the IP are described in the following section.

Functional Description

As shown in Figure 2, UDP40G IP can be divided into three parts, i.e., control block, transmit block, and receive block. The details of each block are described as follows.

Control Block

· Reg

All parameters of the IP are set via register interface which has 5-bit address signals and 32-bit data signals. The timing diagram of the Register interface is similar to a single-port RAM interface, as shown in Figure 6. The write and read address are the same signal. Table 2 provides a description of each register.

Table 2: Register map Definition

RegAddr [4:0]	Reg Name	Dir	Bit	Description
00000b	RST	Wr /Rd	[0]	Reset IP. 0b: No reset, 1b: Reset. Default value is 1b. Once the network parameters have been assigned, the user can execute system initialization by setting this register to 1b and then 0b. This action loads the parameters into the IP. If the user needs to update certain parameters, this process must be repeated by setting this register to 1b and then 0b again. The RST register controls the following network parameters: SML, SMH, DML, DMH, DIP, SIP, DPN, SPN and SRV.
00001b	CMD	Wr	[0]	User command. Set 1b to start sending data. In order to start a new operation by setting this register, the system must be in the Idle state. To confirm that the system is not busy, the user needs to read Busy signal or bit[0] of CMD register, which must be equal to 0b.
00001b	CMD	Rd	[0]	System busy flag. 0b: Idle, 1b: IP is busy during initialization or send command. This signal is also mapped as Busy (IP output signal).
00010b	SML	Wr /Rd	[31:0]	Define 32-bit lower MAC address (bit [31:0]) for this IP. To update this value, the IP must be reset by RST register.
00011b	SMH	Wr /Rd	[15:0]	Define 16-bit upper MAC address (bit [47:32]) for this IP. To update this value, the IP must be reset by RST register.
00100b	DIP	Wr /Rd	[31:0]	Define 32-bit target IP address. To update this value, the IP must be reset by RST register.
00101b	SIP	Wr /Rd	[31:0]	Define 32-bit IP address for this IP. To update this value, the IP must be reset by RST register.
00110b	DPN	Wr /Rd	[31:0]	[15:0]-Define 16-bit target port number for the UDP40G IP to send data. [31:16]-Define 16-bit target port number for the UDP40G IP to receive data. To update this value, the IP must be reset by RST register.
00111b	SPN	Wr /Rd	[15:0]	Define 16-bit port number for this IP. To update this value, the IP must be reset by RST register.

RegAddr [3:0]	Reg Name	Dir	Bit	Description
01000b	TDL	Wr	[31:0]	Define 32 lower bits (bit[31:0]) of 48-bit total Tx data length in byte unit. The value must be aligned to 32-byte because bit[4:0] are not used. Valid range is 32-0xFFFF_FFFF_FFE0. The 16 upper bits (bit[47:32]) are assigned in TDH register (01101b). The user must first set this register before setting CMD register=1b. When the IP executes the command and asserts Busy to 1b, the system will read this register, allowing the user to subsequently set the TDL/TDH register for the next command. If the same TDL/TDH is used in the subsequent command, the user is not required to set TDL/TDH again.
01000b	TDL	Rd	[31:0]	32 lower bits of 48-bit remaining transfer length in byte unit which does not transmit.
01001b	TMO	Wr	[31:0]	Define timeout value for awaiting the return of an ARP reply packet after sending an ARP request packet. The counter runs based on the Clk signal provided by the user, with the timer unit being equal to 1/Clk. If the ARP reply packet is not received in the specified time, IntOut will be asserted to 1b. The optimal value depends on system requirements and network characteristics, but it is typically set to 1 second or larger.
01001b	TMO	Rd	[31:0]	The details of timeout interrupt are shown in TMO[0] and TMO[10:8]. [0]-Timeout from not receiving ARP reply packet After timeout, the IP resends ARP request until ARP reply is received. [8]-Asserted when Rx data buffer is full. After that, all received packet are ignored until the buffer is not full. [9]-Asserted when UDP checksum of the received packet is error. [10]-Asserted when bit257 of MacRxFfRdData is set to 1b, indicating an EMAC error.
01010b	PKL	Wr /Rd	[15:0]	UDP data length of each Tx packet in byte unit. The value must be aligned to 16-byte because bit[4:0] are not used. Valid from 32-8960. Default value is 1472 byte, which is the maximum size of non-jumbo frame and aligned to 32-byte. During running Send data command (Busy=1b), the user must not set this register. Similar to TDL/TDH register, the user does not need to set PKL register again if the next command uses the same packet length.
01101b	TDH	Wr	[15:0]	Define 16 upper bits (bit[47:32]) of 48-bit total Tx data length in byte unit, as described in TDL register.
01101b	TDH	Rd	[15:0]	16 upper bits of 48-bit remaining transfer length in byte unit which does not transmit, as described in TDL register.
01110b	SRV	Wr/ Rd	[1:0]	00b: Client mode (default). When the RST register changes from 1b to 0b, the IP sends an ARP request to obtain the Target MAC address from the ARP reply returned by the target device. The IP busy signal is de-asserted to 0b after receiving the ARP reply. 01b: Server mode. When RST register changes from 1b to 0b, the IP waits for an ARP request from the target to obtain Target MAC address. After receiving the ARP request, the IP generates an ARP reply and then de-asserts the IP busy signal to 0b. 1Xb: Fixed MAC Mode. When the RST register changes from 1b to 0b, the IP updates all internal parameters and then de-asserts IP busy to 0b. Target MAC address is loaded through the DML/DMH register. Note: In Server mode, when RST register changes from 1b to 0b, the target device must resend an ARP request for the UD40G IP to complete the IP initialization process.
01111b	VER	Rd	[31:0]	IP version
10000b	DML	Wr /Rd	[31:0]	Define 32-bit lower target MAC address (bit [31:0]) for this IP when SRV[1]=1b (Fixed MAC). To update this value, the IP must be reset by RST register.
10001b	DMH	Wr /Rd	[15:0]	Define 16-bit upper target MAC address (bit [47:32]) for this IP when SRV[1]=1b (Fixed MAC). To update this value, the IP must be reset by RST register.

· UDP Stack

The UDP stack is responsible for controlling the modules involved in interfacing with the user and transferring packets via EMAC. The IP operation involves two phases - IP initialization and data transfer. After the RST register transitions from 1b to 0b, the initialization phase begins. The SRV[1:0] are used to set the initialization mode, which can be Client mode, Server mode, or Fixed MAC mode. The UDP stack reads the parameters from the Reg module and sets them in the Transmit and Receive blocks for packet transfer with the target device. Once initialization is completed, the IP enters the data transfer phase.

The UDP40G IP allows for simultaneous data transfer in both Tx and Rx directions with the target device. During sending data, the Busy signal is set to 1b. It is de-asserted to 0b once the sending process is completed. To transmit data, the user data is stored in the Tx data and Tx packet buffers. The Packet Builder uses the user-defined network parameters to build UDP header, and then the data of Tx data buffer is appended to the UDP packet. The Transmit block then sends the UDP packet to the target device via Ethernet MAC.

When the Receive block receives data, the Busy signal is not asserted. The extracted UDP data from the received packet is forwarded to the user without generating any packet to be returned to the target device. The Tx and Rx of UDP/IP are processed individually to achieve optimal performance in both directions.

Table 3: TxBuf/RxBufBitWidth Parameter description

Value of BitWidth	Buffer Size	TxBufBitWidth	RxBufBitWidth
9	16KB	Valid	Valid
10	32KB	Valid	Valid
11	64KB	Valid	Valid

Transmit Block

Transmit block contains Tx data buffer whose size can be adjusted through parameter assignment. The minimum size of this buffer is limited by the transmit packet size set by the PKL register. Data from the Tx data buffer is split into packets based on the packet size and stored in the Tx packet buffer. UDP header is constructed using the network parameters from the Reg module and then combined with the UDP data from the Tx packet buffer to form a complete UDP packet. The data in the Tx data buffer is flushed after the packet is transmitted to EMAC successfully. Once the Send data command is completed, the user can initiate the next command.

· Tx Data Buffer

The size of this buffer is determined by the “TxBufBitWidth” parameter of the IP, with valid value ranging from 9-11, which corresponds to the address size of a 256-bit buffer as shown in Table 3. To ensure sustainable transmission of data to EMAC, the buffer size should be at least twice the size of the Tx Packet Size set in the PKL register. By filling the buffer with data that is at least two times of the PKL value, the UDP40G IP will have a sufficient amount of data to transmit. This results in the best transmit performance on 40G Ethernet. Increasing the size of the buffer increases the possibility that at least two packet data will be available for UDP40G IP use.

· Tx Packet Buffer

This buffer stores at least one complete packet before forwarding a packet to Ethernet MAC.

· Packet Builder

The UDP packet consists of a header and data. The Packet builder receives network parameters from the Reg module and uses them to construct the UDP header. The UDP and IP checksum are also calculated for the header. Once the header is fully constructed, it is combined with the data from the Tx packet buffer and then transmitted to the Ethernet MAC.

Receive Block

The Receive block contains the Rx data buffer, which stores the data received from the target device. The received data is stored in the buffer when the header in the packet matches the expected value, set by the network parameters inside the Reg module, and when the IP and UDP checksum are correct. If any of these conditions are not met, the received packet is rejected. Increasing the size of the Rx data buffer enhances the chances of avoiding lost packets due to user logic pausing for too long while reading data.

· Rx Buffer

This is temporary buffer that is used to hold incoming packets from Ethernet MAC in cases where the previous packet has not yet been completely processed.

· Packet Filtering

This module is responsible for verifying the header of the Rx packet to determine its validity. The packet will be valid if all following conditions are met.

(1) The network parameters must match the values set in the Reg module, such as the MAC address, IP address, and Port number.

(2) The packet must either be an ARP packet or a UDP/IPv4 packet.

(3) The IP header length must be valid, with the IP length being equal to 20 bytes.

(4) The IP data length matches to the UDP data length.

(5) Both the IP checksum and UDP checksum must be correct.

Note: UDP checksum is not verified for fragment packet.

(6) In case of fragment packet, the order of received packet must be correct. The packet is rejected when the fragment offset is skipped value.

· Packet Splitter

The purpose of this module is to extract UDP data from incoming packets and store it in the Rx data buffer, after removing the packet header.

· Rx Data Buffer

The size of the Rx data buffer is determined by the “RxBufBitWidth” parameter of the IP and can range from 9 – 11 (16KB to 64KB). It is recommended to set the buffer size to be equal to or greater than two times of the data size in the received packet. To ensure that data is not lost, user logic must read the data from the buffer to keep the free space size of the buffer to be greater than the data size in the received packet. Increasing the size of the buffer increases the possibility of having enough free space to store new data from the target device.

User Block

The core engine of the user module can be designed by state machine to set the command and the parameters through the Register interface. Additionally, the status can be monitored to ensure that the operation has been completed without any errors. The data path can also be connected to the FIFO for sending or receiving data with the IP.

40G/50G Ethernet Subsystem

The Xilinx IP core implements the MAC and PCS/PMA layers for BASE-R modes to work with the UltraScale and UltraScale+ FPGAs. More information can be found on the following website.

https://www.xilinx.com/products/intellectual-property/ef-di-50gemac.html

Core I/O Signals

Descriptions of all parameters and I/O signals are provided in Table 4 and Table 5. The EMAC Interface is 256-bit FWFT FIFO interface.

Table 4: Core Parameters

Name	Value	Description
TxBufBitWidth	9-11	Setting Tx data buffer size. The value is referred to address bus size of this buffer.
RxBufBitWidth	9-11	Setting Rx data buffer size. The value is referred to address bus size of this buffer.

Table 5: Core I/O Signals

Signal	Dir	Description
Common Interface Signal
RstB	In	Reset IP core. Active Low.
Clk	In	User clock. The clock frequency must be equal to or greater than 200 MHz to maintain good performance.
User Interface
RegAddr[4:0]	In	Register address bus. Valid when RegWrEn=1b in Write process.
RegWrData[31:0]	In	Register write data bus. Valid when RegWrEn=1b.
RegWrEn	In	Register write enable. Valid at the same clock as RegAddr and RegWrData.
RegRdData[31:0]	Out	Register read data bus. Valid in the next clock after RegAddr is valid.
Busy	Out	IP busy status (0b-Idle, 1b-IP is busy when executing the initialization or send data process)
IntOut	Out	Timer interrupt. Set to 1b for 1 clock cycle when timeout is detected or Rx packet is ignored. More details of Interrupt status could be checked from TMO[10:0] register.
Tx Data Buffer Interface
UDPTxFfFull	Out	Asserted to 1b when Tx data buffer is full. User needs to stop writing data within 4 clock cycles after this flag is asserted to 1b.
UDPTxFfWrCnt[10:0]	Out	Data counter in 256-bit unit of Tx data buffer to show the amount of data in Tx data buffer.
UDPTxFfWrEn	In	Write enable to Tx data buffer. Asserted to 1b to write data to Tx data buffer.
UDPTxFfWrData[255:0]	In	Write data to Tx data buffer. Valid when UDPTxFfWrEn=1b.
Rx Data Buffer Interface
UDPRxFfRdCnt[10:0]	Out	Data counter of Rx data buffer to show the number of received data in 256-bit unit.
UDPRxFfLastRdCnt[4:0]	Out	Remaining byte of the last data in Rx data buffer when total amount of received data in the buffer is not aligned to 32-byte unit. User cannot read the data until all 32-byte data is received.
UDPRxFfRdEmpty	Out	Asserted to 1b when Rx data buffer is empty. User needs to stop reading data immediately when this signal is asserted to 1b.
UDPRxFfRdEn	In	Asserted to 1b to read data from Rx data buffer.
UDPRxFfRdData[255:0]	Out	Data output from Rx data buffer. Valid in the next clock cycle after UDPRxFfRdEn is asserted to 1b.

Signal	Dir	Description
MAC FIFO Interface (FWFT mode)
MacTxFfWrCnt[15:0]	In	Write data counter for the MacTxFIFO in 256-bit. Used to monitor the FIFO full status. When the FIFO becomes full, data transmission temporarily halts. If the data count of FIFO is less than 16 bits, the upper bits should be padded with 1b to complete the 16-bit count.
MacTxFfWrData[255:0]	Out	Write data bus to the MacTxFIFO. Valid when MacTxFfWrEn=1b.
MacTxFfWrEn	Out	Asserted to 1b to write data to the MacTxFIFO. It remains set to 1b from the first data of the packet to the last data of the packet, ensuring continuous transmission of each Tx packet.
MacTxLastByteEn[31:0]	Out	Data byte enable of the last data within each Tx packet. It is valid when both MacTxEnd and MacTxFfWrEn are set to 1b. In case of the UDP40G IP, this signal can be assigned by two values: 0x0FFF_FFFF or 0x0000_03FF.
MacTxSizeData[15:0]	Out	Tx packet size in 256-bit unit. This value remains stable while MacTxFfWrEn is set to 1b. Bits[15:11] are always set to 0.
MacTxEnd	Out	Asserted to 1b to indicate the final data of each Tx packet.
MacRxFfEmpty	In	Empty flag of the MacRxFIFO. Asserted to 1b when there is no remaining data in the MacRxFIFO.
MacRxFfRdEn	Out	Asserted to 1b to read data from the MacRxFIFO when the MacRxFfEmpty is set to 0b.
MacRxFfRdData[257:0]	In	Read data output from the MacRxFIFO. According to the FWFT FIFO characteristic, this signal is valid when MacRxFfRdEn is set to 1b. Each received data is defined as follows. [255:0]: 256-bit received data from the Ethernet MAC. [256]: Set to 1b to indicate the final data in each Rx packet from the Ethernet MAC. [257]: 0b-normal packet, 1b-error packet. This bit is valid with the assertion of bit[256] to 1b, which indicates the final data.

Timing Diagram

IP Initialization

After the RST register value is changed from 1b to 0b, the initialization of UDP40G IP is initialized. Three modes can be executed, Client mode (SRV=00b), Server mode (SRV=01b), and Fixed MAC mode (SRV=1Xb). The information on each mode is presented in the timing diagram below.

Figure 3: IP Initialization in Client mode

As shown in Figure 3, in Client mode, the UDP40G IP sends an ARP request packet and waits for an ARP reply packet returned from the target device. Target MAC address is extracted from ARP reply packet. Upon completion, the Busy signal is de-asserted to 0b.

Figure 4: IP Initialization in Server mode

As shown in Figure 4, after reset process in Server mode is completed, the UDP40G IP waits for an ARP request packet from the target device. Upon receipt, the UDP40G IP generates an ARP reply packet. The Target MAC address is extracted from ARP request packet. Once the ARP reply packet has been transmitted, the Busy signal is de-asserted to 0b.

Figure 5: IP Initialization in Fixed MAC mode

As shown in Figure 5, after reset process in Fixed MAC mode is completed, the UDP40G IP updates all parameters from the registers. The Target MAC address is loaded from DML and DMH register. Once this process is finished, the Busy signal is de-asserted to 0b.

Register Interface

The Register interface is responsible for setting and monitoring all control signals and network parameters during operation. The timing diagram of the interface is similar to that of Single-port RAM, which shares the address bus for write and read access, and has a read latency time of one clock cycle. A Register map of this interface is provided in Table 2.

As shown in Figure 6, to write to the register, the user sets RegWrEn to 1b with the valid values for RegAddr and RegWrData. Before setting RegWrEn to 1b, please confirm that RstB is de-asserted to 1b for at least 4 clock cycles. To read from the register, the user only sets RegAddr, and RegRdData becomes valid in the next clock cycle.

Figure 6: Register interface timing diagram

As shown in Figure 7, before setting the CMD register to initiate a new command operation, the Busy flag must be equal to 0b to confirm that IP is in Idle status. After setting the CMD register, the Busy flag is asserted to 1b and de-asserted to 0b when the command is completed.

Figure 7: CMD register timing diagram

Tx FIFO Interface

Tx FIFO interface provides two control signals for the flow control, the full flag (UDPTxFfFull) and the write data counter (UDPTxFfWrCnt). UDPTxFfWrCnt is updated after asserting UDPTxFfWrEn for two clock cycles. UDPTxFfFull serves as an indicator of when the internal buffer is almost full and is asserted before it reaches its capacity. It is recommended to pause sending data within four clock cycles after UDPTxFfFull is asserted. Figure 8 shows an example timing diagram for the Tx FIFO interface.

Figure 8: Tx FIFO interface timing diagram

1) When the IP is in reset state (RST[0] register=1b), the full flag (UDPTxFfFull) is set to 1b, preventing data from being sent by the user. Once the reset is released (RST[0]=0b), UDPTxFfFull is set to 0b, allowing the user to write data to the IP.

2) To write data, the user needs to set UDPTxFfWrEn to 1b along with the write data on UDPTxFfWrData signal.

3) If UDPTxFfFull is set to 1b, the user must pause sending data by de-asserting UDPTxFfWrEn to 0b within 4 clock cycles.

Rx FIFO Interface

The Rx FIFO interface is used to retrieve data stored in the Rx data buffer. To determine if data is available for reading, the Empty flag (UDPRxFfEmpty) is monitored, and the read enable signal (UDPRxFfRdEn) is then asserted to access the data, like a typical FIFO read interface, as illustrated in as shown in Figure 9.

Figure 9: Rx FIFO interface timing diagram using Empty flag

1) After the IP finishes reset process, there is no data in Rx data buffer and UDPRxFfEmpty is set to 1b.

2) Check the UDPRxFfEmpty flag to confirm data availability. When data is ready (UDPRxFfEmpty=0b), UDPRxFfRdEn can be set to 1b to read data from the Rx data buffer simultaneously.

3) The UDPRxFfRdData signal is valid in the next clock cycle.

4) Reading data must be immediately paused by setting UDPRxFfRdEn=0b when UDPRxFfEmpty is equal to 1b.

Figure 10: Rx FIFO interface timing diagram using read counter

When the user logic reads data in burst mode, the UDP40G IP provides a read data counter signal to indicate the total amount of data stored in the Rx data buffer in bytes. For instance, in Figure 10, there are five units of data available in the Rx data buffer. Therefore, the user can set UDPRxFfRdEn to 1b for five clock cycles to read all the data from the Rx data buffer. The latency time to update UDPRxFfRdCnt after setting UDPRxFfRdEn to 1b is two clock cycles.

MAC FIFO Interface

The UDP40G IP employs a 256-bit FWFT FIFO interface for transferring packets with the Ethernet MAC within the User clock domain. Consequently, an adapter logic incorporating two asynchronous FWFT FIFOs is integrated to manage clock domain crossing and to transform data stream interface into a 256-bit AXI4-ST, the user interface for the 40G Ethernet Subsystem. Through the incorporation of multiplexers, multiple UDP40G IPs can be linked to this adapter logic to support multiple UDP sessions. Further details regarding the 256-bit TxMACFIFO I/F and RxMACFIFO I/F are provided below.

Figure 11: An adapter logic connecting between UDP40G IP and Ethernet MAC

Before initiating packet transmission, the UDP40G IP checks MacTxFfWrCnt to ensure adequate free space within the MacTxFIFO for storing a packet. Following this verification, MacTxFfWrEn is consistently set to 1b to initiate transmission, continuing from the first data of the packet to the last data of the packet. During packet transmission, MacTxSizeData maintains its value, representing the total data size of the packet in 256-bit unit. An example of timing diagram to show the UDP40G IP’s packet transmission with a packet size of ‘n’ is provided in Figure 12.

Figure 12: TxMACFIFO interface timing diagram

1) When there is adequate free space within the MacTxFIFO to store the n-data packet, confirmed by MacTxFfWrCnt being less than (65535 – n), the UDP40G IP initiates packet transmission. MacTxFfWrEn is set to 1b and the first data of the packet (D0) is placed on MacTxFfWrData. The packet transmission continues seamlessly with MacTxFfWrEn asserted until the final data of the packet (Dn-1) is transmitted.

2) Throughout the packet transmission process, the transmit packet size remains available for reading on MacTxSizeData.

3) To transmit the last data of the packet, both MacTxEnd and MacTxFfWrEn are set to 1b. Additionally, MacTxLastByteEn signal is valid in this clock cycle, indicating the number of valid bytes for the last data of the packet.

Figure 13 shows the example of MacRxFIFO interface when Rx packet size is equal to n. MacRxFfEmpty is applied to monitor data status in MacRxFIFO. The interface uses FWFT FIFO characteristic, so MacRxFfRdData is valid at the same clock as MacRxFfRdEn=’1’.

Figure 13: RxMACFIFO interface timing diagram

1) Upon the MacRxFfEmpty signal being de-asserted to 0b, the UDP40G IP initiates the first data transfer of a received packet (D0). MacRxFfRdEn is set to 1b to commence data retrieval, and MacRxFfRdData is valid within the same clock cycle, following the FWFT FIFO characteristic. The 256-bit received data is placed on bits[255:0] of MacRxFfRdData.

2) While reading the packet, if data is not yet available, as indicated by MacRxFfEmpty being equal to 1b, MacRxFfRdEn is toggled to 0b to momentarily pause data retrieval within the same clock cycle.

3) Upon the transfer of the last data of the packet (Dn-1), bit256 of MacRxFfRdData is set to 1b. Additionally, during this clock cycle, bit257 of MacRxFfRdData is valid to show error status of this packet.

4) After the last data of the packet is transferred, MacRxFfRdEn is reset to 0b for 8 clock cycles, allowing sufficient time for IP post-processing of the packet.

Example usage

Client mode (SRV[1:0] = 00b)

The procedure for configuring the registers to enable data transfer in Client mode is outlined below.

1) Set the RST register to 1b to reset the IP.

2) Set the SML/SMH registers for MAC address, the DIP/SIP registers for IP address, and the DPN/SPN registers for port number.

3) Set the RST register to 0b to start the IP initialization process. Subsequently, the UDP40G IP will send an ARP request packet to obtain the Target MAC address from the ARP reply packet. Upon completion of the initialization process, the Busy signal is de-asserted to 0b.

4) a. For transmitting data, configure the TDL/TDH registers (total transmit length) and the PKL register (packet size). Then, set the CMD register to 1b to initiate data transmission. The user can transmit data to the UDP40G IP via the TxFIFO interface either before or after setting the CMD register. Upon the command completion, the Busy flag is de-asserted to 0b. Subsequently, the user can configure new values to the TDL/TDH/PKL registers and set the CMD register to 1b to start the next transmission.

b. For receiving data, the user should monitor the RxFIFO status and read data until the RxFIFO becomes empty.

Server mode (SRV[1:0] = 01b)

In Server mode, the MAC address is derived from the ARP request packet rather than the ARP reply packet as in Client mode. However, the data transfer process remains identical to that of Client mode. The following steps illustrate an example of Server mode.

1) Set the RST register to 1b to reset the IP.

2) Set the SML/SMH registers for MAC address, the DIP/SIP registers for IP address, and the DPN/SPN registers for port number.

3) Set the RST register to 0b to start the IP initialization process by waiting for an ARP request packet to acquire the Target MAC address. Subsequently, the IP creates an ARP reply packet to transmit back to the target device. Upon completion of the initialization process, the Busy signal is de-asserted to 0b.

4) The remaining step is the same as step 4 of the Client mode configuration.

Fixed MAC mode (SRV[1] = 1b)

In Fixed MAC mode, the MAC Address of the target device is loaded from the DML and DMH registers. The data transfer process remains identical to that of Client and Server modes. The following steps provides an example of how to operate the UDP40G IP in Fixed MAC mode.

1) Set the RST register to 1b to reset the IP.

2) Set the SML/SMH registers for MAC address of UDP40G IP, the DML/DMH registers for the MAC address of the target device, the DIP/SIP registers for IP address, and the DPN/SPN registers for port number.

3) Set the RST register to 0b to start the IP initialization process. Upon completion of the initialization process, the Busy signal is de-asserted to 0b.

4) The remaining step is the same as step 4 of the Client mode configuration.

Verification Methods

The UDP40G IP Core functionality was verified by simulation and also proved on real board design by using ZCU102/ZCU106/KCU105 evaluation board.

Recommended Design Experience

User must be familiar with HDL design methodology to integrate this IP into the system.

Ordering Information

This product is available directly from Design Gateway Co., Ltd. Please contact Design Gateway Co., Ltd. for pricing and additional information about this product using the contact information on the front page of this datasheet.

Revision History

Revision	Date	Description
2.00	7-Mar-24	Extend register address to 5 bits and update register map in Table 2. Add Figure 5 to show Fixed MAC mode initialization.
1.01	2-Oct-20	Update company info
1.00	21-Oct-19	New release