Applications
Accelerate 100G Ethernet TCP/IP data transfer by moving the TCP/IP stack from host software into pure FPGA hardware logic. The reference design combines DG TOE100G-IP with Silicom PacketMover to provide two dedicated high-speed TCP sessions while preserving standard NIC functionality.
TOE100G-IP implements the complete TCP/IP protocol stack in pure FPGA hardware logic — no CPU cycles, no external memory. Deterministic, always-on performance at 100G line rate.
The number of TCP sessions is fully scalable — users can configure and adjust session count by integrating multiple TOE100G-IP cores themselves. The demo uses two sessions as a working example, but the architecture is not limited to that.
Non-accelerated traffic continues through the Standard NIC interface to the host CPU. TCP offload and normal NIC operation coexist on the same FPGA card without conflict.
| FPGA Card | Silicom fb2CG@KU15P — Xilinx Kintex UltraScale+ XCKU15P |
| Network Ports | 2 × QSFP28 connectors — 100G Ethernet |
| Host Interface | PCIe Gen3 × 16 |
| Host OS | Ubuntu 20.04 LTS |
| IP Cores | TOE100G-IP × 2 (Design Gateway) — Full TCP/IP Offload Engine |
| Framework | Silicom PacketMover FPGA Acceleration Platform |
| Reference Design | TOE100G-IP on Silicom NIC Reference Design |
| Peak Throughput | 12 GB/s TX + 12 GB/s RX — 100G Ethernet line rate |
Performance test results measured on the TOE100G-IP + Silicom PacketMover system with the fb2CG@KU15P FPGA card.
tcpdatatest for half duplex, tcp_client_txrx_single for full duplex) on the target FPGA board to initiate the TCP transfer.
For full documentation, register map, and hardware design files, refer to the links below.
Watch the TOE100G-IP + Silicom PacketMover system in action, demonstrating full TCP/IP hardware offload at 100G Ethernet line rate with zero CPU involvement.
For full documentation, register map, and hardware design files, refer to the links in the How to Use section above.
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