Connecting Multiple NVMe SSDs via PCIe Switch with NVMeSW-IP

IP Core Capabilities

Key Features

Full Hardware NVMe Engine

All NVMe protocol processing is implemented entirely in FPGA logic — no CPU cycles consumed during data transfer, ensuring deterministic, wire-speed performance.

PCIe Switch Support

NVMeSW-IP communicates through a PCIe switch to manage multiple downstream NVMe SSD ports, enabling concurrent multi-drive access from a single FPGA PCIe upstream port.

Simple User Interface

The IP core exposes a straightforward dgIF-typeS command/data interface. Users issue Write, Read, Identify, SMART, Flush, and Shutdown commands without handling NVMe protocol details.

Standard PCIe Hard IP Integration

Integrates with the vendor-supplied PCIe Hard IP block (AXI4-S for AMD / Avalon-ST for Altera), maintaining full compatibility with both major FPGA ecosystems.

Design Advantages

Why Use FPGA & NVMeSW-IP?

General-purpose CPU-based NVMe drivers are not designed for deterministic, high-throughput, multi-drive scenarios. FPGA-based NVMe control unlocks capabilities that no software stack can match.

Zero Overhead

Zero CPU Overhead During Transfer

NVMeSW-IP handles all NVMe queue management and DMA in hardware. The onboard CPU (or SoC processor) is free to run application logic while storage transfers proceed autonomously in parallel.

Sustained Performance

Maximum & Sustained Throughput

Hardware pipeline logic delivers maximum throughput at a stable, sustained rate. Each function is implemented as a dedicated logic block — no contention, no scheduling overhead, and no performance drop under continuous load.

Reconfigurable

Scalable Flexibility via Reconfigurable FPGA

The IP core integrates directly with user-defined FPGA logic within the same fabric, eliminating inter-chip latency. The number of PCIe switch cards, SSDs, and NVMeSW-IP instances can be freely adjusted at any development stage without hardware replacement.

Target Applications

The combination of deterministic timing, high bandwidth, and rugged FPGA deployment makes NVMeSW-IP particularly well-suited for demanding sectors.

✈ Aerospace & Defense

Mission-Critical Recording & Multi-Host Storage
Sensor and mission data is distributed across NVMe SSDs as large partitions. Multiple hosts — FPGA, GPU, SoC, or external server — collaborate over the PCIe fabric. The FPGA drives deterministic, full-performance data movement; GPU/SoC handles AI inference, image processing, radar signal processing, or post-analysis; and a server manages configuration, firmware updates, or mission reconfiguration.

Airborne Black-Box / Flight Data Recorder

No-Gap Lossless Write — Continuous lossless write of avionics, video, and flight data to multiple NVMe SSDs with zero recording gaps. FPGA controls high-speed writes; an external host retrieves or reconfigures data post-mission.

Radar & Electronic Warfare

Wideband Data Capture at Multi-GB/s Rates — Multi-GB/s wideband RF capture striped across SSDs. FPGA performs real-time filtering; GPU/SoC runs target detection, spectrum analysis, or EW classification.

Satellite Payload Storage

Downlink Buffering and Retransmission — Camera, sensor, and comm data buffered to NVMe arrays before downlink. FPGA manages high-speed storage; SoC/GPU handles compression, encryption, and packetization.

📈 Test & Instrumentation

High-Throughput Recording & Signal Analysis
The FPGA acts as the real-time data engine — receiving high-speed streams from digitizers, RF front ends, or test equipment and writing in parallel across multiple NVMe SSDs. GPU or SoC handles complex analysis such as waveform processing, spectrum analysis, AI classification, or protocol inspection. A host server or PC connects for test configuration, sequence control, data retrieval, or FPGA reconfiguration.

High-Speed Data Acquisition

Gapless Capture for Oscilloscopes and Digitizers — NVMeSW-IP streams samples directly from FPGA logic to multiple NVMe SSDs for gapless, long-duration recording — no lost transients, no large memory buffers required.

RF Signal Recording & Analysis

Wideband Streaming for Spectrum and Protocol Test — Wideband RF and I/Q data is recorded to NVMe SSD arrays at multi-GB/s rates. FPGA handles real-time preprocessing; GPU or SoC performs spectrum analysis, modulation analysis, or anomaly detection.

Automated Test Equipment (ATE)

Large Test-Data Buffering, Replay and Post-Analysis — Multiple NVMe SSDs form a scalable high-speed buffer; FPGA executes deterministic test transfers, while a host manages device programming, test flow, and result collection.

Technical Specs

System Requirements

FPGA Development Kit	AMD — KCU105, ZCU106, VCU118 Altera — Arria 10 GX Development Kit
PCIe Switch Card	Quattro 400 M.2 NVMe SSD Adapter \| Squid SKU-086-34 NVMe SSD Adapter
NVMe SSDs	NVMe PCIe SSDs (Gen3)
Host PC	Windows or Linux PC for initial programming and monitoring via UART / JTAG
IP Core	NVMeSW-IP (NVMe IP Core for PCIe Switch)
Reference Design	NVMeSW-IP Reference Design

Live Demonstration

Demo & Documentation

AMD

NVMeSW-IP for AMD FPGAs (KCU105, ZCU106, VCU118). Supports AXI4-ST interface to PCIe Hard IP. A free evaluation demo for AMD KCU105 is publicly available.

📄 Data Sheet 📋 Reference Design Manual 📖 Demo Instruction Manual

💾 Free Evaluation Demo

AMD (KCU105)

Download ↓

DEMO VIDEO — AMD