本文へスキップ

The Expert of IP Core & Embedded

Japanese

USB3.0-IP coreFAT32 Data Recorder is available!!

USB3.0-IP

USB3.0-IPcore compliants with the USB 3.0 specification Revision1.0 and work on Altera 5-Series, Cyclone IV, Arria II, Stratix IV FPGA devices.
This IPcore provide link layer, protocol layer. Physical layer interfaces to PHY chip by TI.
DesignGateway provide 1-hour limited sof file for Altera FPGA evaluation board. You can evaluate on Altera FPGA development kit before purchasing the IPcore.


Features

  • Compliant with the USB3.0 specification Revision1.0
  • USB3.0 Host or Device Controller
  • Implement link layer and protocol layer
  • IP core clocks are adjustable (250MHz for PIPE I/F, more than 125MHz for internal)
  • Support 16bit PIPE interface
  • Support IN/OUT end point up to 15 points
    - 1 point for control
    - 7 points each for IN/OUT
  • Support All transmission taps (Control, Bulk, Isochronous and Interrupt transmission)
  • Simple transaction interface with Host processor or DMA interface
  • Able to evaluate on Altera FPGA Development Kit before purchasing the IPcore
  • Go to Registration page to get password
  • USB protocol stack is provided by Macnica Macspire. Able to support Video class (UVC) and Audio class (ADC). Please contact Macnica Macspire

Block diagram (Host)



Document download

Common Documents

Document name Download
USB3.0-IP core Presentation Rev1.1
FAT32 Data Recorder Presentation Rev1.0
AB08-USB3HSMC Board Manual Rev1.2

Document name Cyclone-VE Arria-V GX Cyclone-IV GX Arria-II GX Stratix-IV GX
Host Datasheet Rev1.4
Reference Design Document Rev1.0
Demo Instruction Document  Rev1.2
Evaluation demo file
Get password page
Cyclone V E Arria V GX - - -
Demo Video - - - -
Device Datasheet Rev1.4
Reference Design Document Rev1.1
Demo Instruction Document Rev1.3 -
Evaluation demo file
Get password page
Cyclone V E Arria V GX Cyclone IV GX Arria II GX Stratix IV GX
Demo Video - - -
FAT32
Data
Recorder
(Device)
FAT32 Data Recorder Presentation Rev1.0 - - -
Reference Design Document Rev1.0 - - -
Demo Instruction Document Rev1.0 - - -
Evaluation demo file
Get password page
Cyclone V E Arria V GX - - -
Demo Video - - - -


Free sof file for evaluation

USB3.0(device)-IP
evaluation on Cyclone IV GX
Video Clip on youtube
DesignGateway provide 1-hour limited sof file. You can evaluate USB3.0-IP core on Altera FPGA development kit before purchasing the IP core.
For the evaluation, USB3.0-HSMC adaptor board is necessary.(P/N: AB08-USB3HSMC). Please ask Design Gateway.

Go to Registration page to get password


Performance

USB3.0-IP core can achieve maximum performance of current USB3.0 system.
USB3.0-IP core (external PHY less) evaluation on Stratix IV GX FPGA dev kit
(with AB13-USB3PCIe adaptor board)
USB3.0-IP core Host Reference Design
Support FAT32 commands


Application: FAT32 data recording system (Device Side)

You can easily build FAT32 data recorder system with USB3.0 Device IP core.

System Overview



Features

  • PC recognizes as FAT32 external storage without any driver for Windows or Linux!
  • FAT32 data recorder reference design is available.
  • Free evaluation bit file for Altera FPGA development kits.

Inquiry/Purchase

Part Number Supported Devices

Host IP

USB3H-IP-S4GX (external PHY less) Stratix IV GX
USB3H-IP-S4 Stratix IV
USB3H-IP-A5 Arria V
USB3H-IP-A2 Arria II
USB3H-IP-C4 Cyclone IV
USB3H-IP-C5 Cyclone V

Device IP

USB3D-IP-S4GX (external PHY less) Stratix IV GX
USB3D-IP-S4 Stratix IV
USB3D-IP-A5 Arria V
USB3D-IP-A2 Arria II
USB3D-IP-C4 Cyclone IV
USB3D-IP-C5 Cyclone V
Accessories for evaluation Description
AB08-USB3HSMC USB3.0-HSMC adaptor board for Altera FPGA dev kit.
USB3.0 TypeAtoA cable(1m) is attached.